Welcome to RISCV-BOOM’s documentation!

Contents:

• 1. Introduction and Overview
  • 1.1. The BOOM Pipeline
  • 1.2. The RISC-V ISA
  • 1.3. The Chisel HCL
  • 1.4. Quick-start
  • 1.5. The BOOM Repository
  • 1.6. The Rocket-Chip Repository
• 2. Instruction Fetch
  • 2.1. The Rocket I-Cache
  • 2.2. Fetching Compressed Instructions
  • 2.3. The Fetch Buffer
  • 2.4. The Fetch Target Queue
• 3. Branch Prediction
  • 3.1. The Next-line Predictor (NLP)
  • 3.2. The Backing Predictor (BPD)
• 4. The Decode Stage
  • 4.1. RVC Changes
• 5. The Rename Stage
  • 5.1. The Purpose of Renaming
  • 5.2. The Explicit Renaming Design
  • 5.3. The Rename Map Table
  • 5.4. The Busy Table
  • 5.5. The Free List
  • 5.6. Stale Destination Specifiers
• 6. The Reorder Buffer (ROB) and the Dispatch Stage
  • 6.1. The ROB Organization
  • 6.2. ROB State
  • 6.3. The Commit Stage
  • 6.4. Exceptions and Flushes
• 7. The Issue Unit
  • 7.1. Speculative Issue
  • 7.2. Issue Slot
  • 7.3. Issue Select Logic
  • 7.4. Un-ordered Issue Queue
  • 7.5. Age-ordered Issue Queue
  • 7.6. Wake-up
• 8. The Register Files and Bypass Network
  • 8.1. Register Read
  • 8.2. Bypass Network
• 9. The Execute Pipeline
  • 9.1. Execution Units
  • 9.2. Functional Units
  • 9.3. Branch Unit & Branch Speculation
  • 9.4. Load/Store Unit
  • 9.5. Floating Point Units
  • 9.6. Floating Point Divide and Square-root Unit
  • 9.7. Parameterization
  • 9.8. Control/Status Register Instructions
• 10. The Load/Store Unit (LSU)
  • 10.1. Store Instructions
  • 10.2. Load Instructions
  • 10.3. The BOOM Memory Model
  • 10.4. Memory Ordering Failures
• 11. The Memory System and the Data-cache Shim
• 12. Micro-architectural Event Tracking
  • 12.1. Setup HPM events to track
  • 12.2. Reading HPM counters in software
  • 12.3. Adding your own HPE
  • 12.4. External Resources
• 13. Verification
  • 13.1. RISC-V Tests
  • 13.2. RISC-V Torture Tester
  • 13.3. Continuous Integration (CI)
• 14. Debugging
  • 14.1. FireSim Debugging
  • 14.2. Pipeline Visualization
• 15. Physical Realization
  • 15.1. Register Retiming
  • 15.2. Pipelining Configuration Options
• 16. Future Work
  • 16.1. The Rocket Custom Co-processor Interface (ROCC)
  • 16.2. The Vector (“V”) ISA Extension
• 17. Parameterization
  • 17.1. BOOM Parameters
  • 17.2. Other Parameters
• 18. Frequently Asked Questions
• 19. The BOOM Ecosystem
  • 19.1. Scala, Chisel, Generators, Configs, Oh My!
• 20. Terminology
• 21. Bibliography

Indices and tables

• Index
• Module Index
• Search Page