RISCV-BOOM
stable
Introduction:
The Berkeley Out-of-Order Machine (BOOM)
The BOOM Pipeline
The Chisel Hardware Construction Language
The RISC-V ISA
Rocket Chip SoC Generator
Core Overview:
Instruction Fetch
Branch Prediction
The Decode Stage
The Rename Stage
The Reorder Buffer (ROB) and the Dispatch Stage
The Issue Unit
The Register Files and Bypass Network
The Execute Pipeline
The Load/Store Unit (LSU)
The Memory System
Usage:
Parameterization
The BOOM Development Ecosystem
Debugging
Micro-architectural Event Tracking
Verification
Physical Realization
Other:
Future Work
Frequently Asked Questions
Terminology
RISCV-BOOM
Docs
»
Index
Edit on GitHub
Index
B
|
E
|
F
|
G
|
M
|
N
|
R
|
T
B
Back-end
Backing predictor (BPD)
Bi-Modal Table (BIM)
Branch Rename Snapshot
Branch Target Buffer (BTB)
Branch Unit
E
Execution Unit
F
Fetch Boundary
Fetch Buffer
Fetch Packet
Fetch PC
Fetch Target Queue (FTQ)
Fetch Width
Front-end
Functional Unit
G
Global History Register (GHR)
GShare Predictor
M
Micro-Op (UOP)
N
Next-Line Predictor (NLP)
R
Rename Snapshots
Return Address Stack (RAS)
T
TAGE Predictor
Read the Docs
v: stable
Versions
latest
stable
Downloads
pdf
html
epub
On Read the Docs
Project Home
Builds
Free document hosting provided by
Read the Docs
.