RISCV-BOOM

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Contents:

1. Introduction and Overview
2. Instruction Fetch
3. Branch Prediction
4. The Decode Stage
5. The Rename Stage
6. The Reorder Buffer (ROB) and the Dispatch Stage
7. The Issue Unit
8. The Register Files and Bypass Network
9. The Execute Pipeline
10. The Load/Store Unit (LSU)
11. The Memory System and the Data-cache Shim
12. Micro-architectural Event Tracking
13. Verification
14. Debugging
15. Physical Realization
16. Future Work
17. Parameterization
18. Frequently Asked Questions
19. The BOOM Ecosystem
20. Terminology
21. Bibliography

RISCV-BOOM

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