Welcome to RISCV-BOOM’s documentation!

The Berkeley Out-of-Order Machine (BOOM) is a synthesizable and parameterizable open-source RISC-V out-of-order core written in the Chisel hardware construction language. The goal of this document is to describe the design and implementation of the core as well as provide other helpful information to use the core.


The best way to get started with the BOOM core is to use the Chipyard project template. There you will find the main steps to setup your environment, build, and run the BOOM core on a C++ emulator. Chipyard also provides supported flows for pushing a BOOM-based SoC through both the FireSim FPGA simulation flow and the HAMMER ASIC flow. Here is a selected set of steps from Chipyard’s documentation:

Listing 1 Quick-Start Code
# Download the template and setup environment
git clone https://github.com/ucb-bar/chipyard.git
cd chipyard

# build the toolchain
./scripts/build-toolchains.sh riscv-tools

# add RISCV to env, update PATH and LD_LIBRARY_PATH env vars
# note: env.sh generated by build-toolchains.sh
source env.sh

cd sims/verilator
make CONFIG=LargeBoomConfig


Listing 1 assumes you don’t have riscv-tools toolchain installed. It will pull and build the toolchain for you.

Table of Contents

Indices and tables